PIC24FJ64GU202

Support summary

• Programming - Yes
• Debugging provisions - Yes

ICSP Connection

PIC24FJ64GU202 has more than one pair of PGECx and PGEDx pins. You can use any pair, but you must use them as a pair. For example, if PGEC2 is used for ICSPCLK, then ICSPDAT must be connected to PGED2.

All VSS and VDD pins must be connected. Even if one of these pins is not connected, programming may fail.

ICSP write inhibition

It is possible to configure PIC24FJ64GU202 to inhibit all future ICSP writes. Once this is done, the PIC can never be re-programmed again. It is possible to read the chip with nsread if it is not read-protected.

To inhibit all future ICSP writes, use the following command:

nsprog inhibit-ICSP-write-irreversibly -d PIC24FJ64GU202

This action is irreversible. Once you inhibit the ICSP writes, PIC24FJ64GU202 cannot be re-programmed.

Programming Benchmarks

We have measured time necessary to program and verify PIC24FJ64GU202.

The measurements reflect the time necessary to program/verify the entire chip, including all user programmable memory areas.

Debugging

NSDSP firmware contains all the necessary provisions for debugging PIC24FJ64GU202 and may be debugged when debugging software becomes available.

PIC24FJ64GU202 uses ordered halting, has 6 hardware breakpoints.

Debugging does not consume resources in the user space.

Links

Microchip PIC24FJ64GU202 page