PIC24FJ512GA606

Support summary

• Programming - Yes
• Debugging provisions - Yes

ICSP Connection

PIC24FJ512GA606 has more than one pair of PGECx and PGEDx pins. You can use any pair, but you must use them as a pair. For example, if PGEC2 is used for ICSPCLK, then ICSPDAT must be connected to PGED2.

All VSS and VDD pins must be connected. Even if one of these pins is not connected, programming may fail.

Dual partition architecture

PIC24FJ512GA606 may be used as a regular unpartitioned chip, or it may be divided into two partitions, each of which can be used to boot the device. In the unpartitioned mode, the program memory is used as a single block (0x000000-0x056000). However, in the dual-partition mode, it is divided into two equal parts - active partition (0x000000-0x02b000) and inactive partition (0x400000-0x42b000). Active and inactive partitions may be swapped - see datasheet for details.

Before programming, NSDSP searches the HEX file for the FBOOT configuration register. If it is absent or indicates unpartitioned mode, NSDSP does not partition the chip. If it is found and indicates dual-partition mode, NSDSP partitions the chip and expects that the data to program individual partitions will be in range 0x000000-0x02b000 for the first partition or in range 0x400000-0x42b000 for the second partition. NSDSP will not accept program memory addresses outside these two ranges. After programming, depending on the configuration bits, the partitions may get swapped.

When NSDSP is used to read memory it first determines if the chip is partitioned or not. If the chip is not partitioned, NSDSP reads the memory as a single block. If the chip is partitioned, the first partition is always reported as active (0x000000-0x02b000) and the second partition is always reported as inactive (0x400000-0x42b000) regardless of which partition was actually active at the time of reading.

Such arrangement guarantees consistency - if you read a HEX file from the device, then re-program it onto other device, both devices will have identical programming.

Debugging

NSDSP firmware contains all the necessary provisions for debugging PIC24FJ512GA606 and may be debugged when debugging software becomes available.

PIC24FJ512GA606 uses ordered haliting, has 6 hardware breakpoints.

Debugging does not consume resources in the user space.

Links

Microchip PIC24FJ512GA606 page