PIC24FJ64GA102PIC24FJ64GA104 PIC24FJ64GA106 PIC24FJ64GA108 PIC24FJ64GA110 PIC24FJ64GA202 PIC24FJ64GA204 PIC24FJ64GA306 PIC24FJ64GA308 PIC24FJ64GA310 PIC24FJ64GA406 PIC24FJ64GA410 PIC24FJ64GA412 PIC24FJ64GA702 PIC24FJ64GA704 PIC24FJ64GA705 PIC24FJ64GB002 PIC24FJ64GB004 PIC24FJ64GB106 PIC24FJ64GB108 PIC24FJ64GB110 PIC24FJ64GB202 PIC24FJ64GB204 PIC24FJ64GB406 PIC24FJ64GB410 PIC24FJ64GB412 PIC24FJ64GC006 PIC24FJ64GC010 PIC24FJ96GA006 PIC24FJ96GA008 PIC24FJ96GA010
PIC24FJ64GA102 has more than one pair of PGECx and PGEDx pins. You can use any pair, but you must use them as a pair. For example, if PGEC2 is used for ICSPCLK, then ICSPDAT must be connected to PGED2.
All VSS and VDD pins must be connected. Even if one of these pins is not connected, programming may fail.
Refer to the datasheet for alternative connections of DISVREG pin.
We have measured time necessary to program and verify PIC24FJ64GA102.
|Operation||FCKSM=0x||FCKSM=1x||Programming and Verification||1.7s||2.0s||Programming only||1.6s||1.6s||Verification only||1.2s||1.2s|
The measurements reflect the time necessary to program/verify the entire chip, including all user programmable memory areas.
NSDSP firmware contains all the necessary provisions for debugging PIC24FJ64GA102 and may be debugged when debugging software becomes available.
© 2007-2018 Northern Software Inc. All Rights Reserved.