dsPIC33FJ64GP310
dsPIC33FJ64GP310A dsPIC33FJ64GP706 dsPIC33FJ64GP706A dsPIC33FJ64GP708 dsPIC33FJ64GP708A dsPIC33FJ64GP710 dsPIC33FJ64GP710A dsPIC33FJ64GP802 dsPIC33FJ64GP804 dsPIC33FJ64GS406 dsPIC33FJ64GS606 dsPIC33FJ64GS608 dsPIC33FJ64GS610 dsPIC33FJ64MC202 dsPIC33FJ64MC204 dsPIC33FJ64MC506 dsPIC33FJ64MC506A dsPIC33FJ64MC508 dsPIC33FJ64MC508A dsPIC33FJ64MC510 dsPIC33FJ64MC510A dsPIC33FJ64MC706 dsPIC33FJ64MC706A dsPIC33FJ64MC710 dsPIC33FJ64MC710A dsPIC33FJ64MC802 dsPIC33FJ64MC804dsPIC33FJ64GP310
Support summary
- Programming - Yes
- Debugging provisions - Yes
ICSP Connection
This PIC device is equipped with extremely low endurance flash. The datasheet specification guarantees only 100 erase/write cycles. It is easy to wear the flash out during development.
dsPIC33FJ64GP310 has more than one pair of PGECx and PGEDx pins. You can use any pair, but you must use them as a pair. For example, if PGEC2 is used for ICSPCLK, then ICSPDAT must be connected to PGED2.
All VSS and VDD pins must be connected. Even if one of these pins is not connected, programming may fail.
SDO1 pin will toggle at high frequency during programming. Make sure this does not harm your circuit.
Programming Benchmarks
We have measured time necessary to program and verify dsPIC33FJ64GP310.
| Operation | FCKSM=0x | FCKSM=1x | Programming and Verification | 2.0s | 2.2s | Programming only | 1.9s | 1.9s | Verification only | 1.2s | 1.2s |
|---|
The measurements reflect the time necessary to program/verify the entire chip, including all user programmable memory areas.
Debugging
NSDSP firmware contains all the necessary provisions for debugging dsPIC33FJ64GP310 and may be debugged when debugging software becomes available.
dsPIC33FJ64GP310 uses ordered halting, has 6 hardware breakpoints.
Debugging does not consume resources in the user space.
Links
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