dsPIC33CH64MP502dsPIC33CH64MP503 dsPIC33CH64MP505 dsPIC33CH64MP506 dsPIC33CH64MP508
dsPIC33CH64MP502 has more than one pair of PGECx and PGEDx pins. You can use any pair, but you must use them as a pair. For example, if PGEC2 is used for ICSPCLK, then ICSPDAT must be connected to PGED2.
All VSS and VDD pins must be connected. Even if one of these pins is not connected, programming may fail.
dsPIC33CH64MP502 has two separate cores. The program memory of the slave core is volatile, and is destroyed after power-cycling the device. Yet, it is possible to temporarily program the slave core using nsprog with -n option.
When programming the slave through ICSP, the master should not attempt to program the slave by itself. If the master programs the slave, then ICSP programming is impossible because master will overwrite the data programmed with ICSP.
To read and program the slave core, use the same connection as for programming the master.
The slave core uses alternative S1MCLRx pins for debugging. It may be necessary to add a pull-up to the S1MCLRx pin to successfully access the slave core.
NSDSP firmware contains all the necessary provisions for debugging dsPIC33CH64MP502 and may be debugged when debugging software becomes available.
dsPIC33CH64MP502 uses unordered halting, has 8 hardware breakpoints.
Debugging does not consume resources in the user space.
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