dsPIC33CH128MP502dsPIC33CH128MP503 dsPIC33CH128MP505 dsPIC33CH128MP506 dsPIC33CH128MP508 dsPIC33CH256MP205 dsPIC33CH256MP206 dsPIC33CH256MP208 dsPIC33CH256MP505 dsPIC33CH256MP506 dsPIC33CH256MP508 dsPIC33CH512MP205 dsPIC33CH512MP206 dsPIC33CH512MP208 dsPIC33CH512MP505 dsPIC33CH512MP506 dsPIC33CH512MP508 dsPIC33CH64MP202 dsPIC33CH64MP203 dsPIC33CH64MP205 dsPIC33CH64MP206 dsPIC33CH64MP208 dsPIC33CH64MP502 dsPIC33CH64MP503 dsPIC33CH64MP505 dsPIC33CH64MP506 dsPIC33CH64MP508
dsPIC33CH128MP502 has more than one pair of PGECx and PGEDx pins. You can use any pair, but you must use them as a pair. For example, if PGEC2 is used for ICSPCLK, then ICSPDAT must be connected to PGED2.
All VSS and VDD pins must be connected. Even if one of these pins is not connected, programming may fail.
We have measured time necessary to program and verify dsPIC33CH128MP502.
|Operation||FCKSM=0x||FCKSM=1x||Programming and Verification||2.9s||4.1s||Programming only||2.7s||2.7s||Verification only||2.3s||2.3s|
The measurements reflect the time necessary to program/verify the entire chip, including all user programmable memory areas.
NSDSP firmware contains all the necessary provisions for debugging dsPIC33CH128MP502 and may be debugged when debugging software becomes available.
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