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dsPIC33CH512MP205

ICSP connection

Support summary

  • Programming - Yes
  • Debugging provisions - Yes

ICSP Connection

dsPIC33CH512MP205 has more than one pair of PGECx and PGEDx pins. You can use any pair, but you must use them as a pair. For example, if PGEC2 is used for ICSPCLK, then ICSPDAT must be connected to PGED2.

All VSS and VDD pins must be connected. Even if one of these pins is not connected, programming may fail.

Dual partition architecture

dsPIC33CH512MP205 may be used as a regular unpartitioned chip, or it may be divided into two partitions, each of which can be used to boot the device. In the unpartitioned mode, the program memory is used as a single block (0x000000-0x058000). However, in the dual-partition mode, it is divided into two equal parts - active partition (0x000000-0x02c000) and inactive partition (0x400000-0x42c000). Active and inactive partitions may be swapped - see datasheet for details.

Before programming, NSDSP searches the HEX file for the FBOOT configuration register. If it is absent or indicates unpartitioned mode, NSDSP does not partition the chip. If it is found and indicates dual-partition mode, NSDSP partitions the chip and expects that the data to program individual partitions will be in range 0x000000-0x02c000 for the first partition or in range 0x400000-0x42c000 for the second partition. NSDSP will not accept program memory addresses outside these two ranges. After programming, depending on the configuration bits, the partitions may get swapped.

When NSDSP is used to read memory it first determines if the chip is partitioned or not. If the chip is not partitioned, NSDSP reads the memory as a single block. If the chip is partitioned, the first partition is always reported as active (0x000000-0x02c000) and the second partition is always reported as inactive (0x400000-0x42c000) regardless of which partition was actually active at the time of reading.

Such arrangement guarantees consistency - if you read a HEX file from the device, then re-program it onto other device, both devices will have identical programming.

Multiple Cores

dsPIC33CH512MP205 has two separate cores. The program memory of the slave core is volatile, and is destroyed after power-cycling the device. Yet, it is possible to temporarily program the slave core using nsprog with -n option.

When programming the slave through ICSP, the master should not attempt to program the slave by itself. If the master programs the slave, then ICSP programming is impossible because master will overwrite the data programmed with ICSP.

To read and program the slave core, use the same connection as for programming the master.

The slave core uses alternative S1MCLRx pins for debugging. It may be necessary to add a pull-up to the S1MCLRx pin to successfully access the slave core.

ICSP write inhibition

It is possible to configure dsPIC33CH512MP205 to inhibit all future ICSP writes. Once this is done, the PIC can never be re-programmed again. It is possible to read the chip with nsread if it is not read-protected.

To inhibit all future ICSP writes, use the following command:

nsprog inhibit-ICSP-write-irreversibly -d dsPIC33CH512MP205

This action is irreversible. Once you inhibit the ICSP writes, dsPIC33CH512MP205 cannot be re-programmed.

Debugging

NSDSP firmware contains all the necessary provisions for debugging dsPIC33CH512MP205 and may be debugged when debugging software becomes available.

dsPIC33CH512MP205 uses unordered halting, has 8 hardware breakpoints.

Debugging does not consume resources in the user space.

Links

Microchip dsPIC33CH512MP205 page

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