PIC24HJ64GP502
PIC24HJ64GP504 PIC24HJ64GP506 PIC24HJ64GP506A PIC24HJ64GP510 PIC24HJ64GP510APIC24HJ64GP502
Support summary
ICSP Connection
PIC24HJ64GP502 has more than one pair of PGECx and PGEDx pins. You can use any pair, but you must use them as a pair. For example, if PGEC2 is used for ICSPCLK, then ICSPDAT must be connected to PGED2.
All VSS and VDD pins must be connected. Even if one of these pins is not connected, programming may fail.
Programming Benchmarks
We have measured time necessary to program and verify PIC24HJ64GP502.
Operation | FCKSM=0x | FCKSM=1x | Programming and Verification | 2.1s | 2.3s | Programming only | 1.9s | 2.0s | Verification only | 1.2s | 1.2s |
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The measurements reflect the time necessary to program/verify the entire chip, including all user programmable memory areas.
Debugging
NSDSP firmware contains all the necessary provisions for debugging PIC24HJ64GP502 and may be debugged when debugging software becomes available.
PIC24HJ64GP502 uses ordered halting, has 2 hardware breakpoints.
Debugging does not consume resources in the user space.
Links
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