dsPIC33EP512MU810dsPIC33EP512MU814 dsPIC33EP64GP502 dsPIC33EP64GP503 dsPIC33EP64GP504 dsPIC33EP64GP506 dsPIC33EP64GS502 dsPIC33EP64GS504 dsPIC33EP64GS505 dsPIC33EP64GS506 dsPIC33EP64GS708 dsPIC33EP64GS804 dsPIC33EP64GS805 dsPIC33EP64GS806 dsPIC33EP64GS808 dsPIC33EP64MC202 dsPIC33EP64MC203 dsPIC33EP64MC204 dsPIC33EP64MC206 dsPIC33EP64MC502 dsPIC33EP64MC503 dsPIC33EP64MC504 dsPIC33EP64MC506
dsPIC33EP512MU810 has more than one pair of PGECx and PGEDx pins. You can use any pair, but you must use them as a pair. For example, if PGEC2 is used for ICSPCLK, then ICSPDAT must be connected to PGED2.
All VSS and VDD pins must be connected. Even if one of these pins is not connected, programming may fail.
dsPIC33EP512MU810 is more sensitive to cross-talk between PGEC and PGED lines than other PIC devices. This may lead to programming failures, such as inability to connect or various verification failures. One of the methods to improve connectivity is to connect a small 20pF capacitor between PGEC line and VSS as close to the chip as possible. A bigger capacitor may be used, however you will have to decrease ICSP communication speed.
We have measured time necessary to program and verify dsPIC33EP512MU810.
|Operation||FCKSM=0x||FCKSM=1x||Programming and Verification||10.9s||14.4s||Programming only||10.9s||10.9s||Verification only||9.1s||9.1s|
The measurements reflect the time necessary to program/verify the entire chip, including all user programmable memory areas.
NSDSP firmware contains all the necessary provisions for debugging dsPIC33EP512MU810 and may be debugged when debugging software becomes available.
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