PIC24EP512GP202
PIC24EP512GP204 PIC24EP512GP206 PIC24EP512GP806 PIC24EP512GU810 PIC24EP512GU814 PIC24EP512MC202 PIC24EP512MC204 PIC24EP512MC206 PIC24EP64GP202 PIC24EP64GP203 PIC24EP64GP204 PIC24EP64GP206 PIC24EP64MC202 PIC24EP64MC203 PIC24EP64MC204 PIC24EP64MC206PIC24EP512GP202
Support summary
ICSP Connection
PIC24EP512GP202 has more than one pair of PGECx and PGEDx pins. You can use any pair, but you must use them as a pair. For example, if PGEC2 is used for ICSPCLK, then ICSPDAT must be connected to PGED2.
All VSS and VDD pins must be connected. Even if one of these pins is not connected, programming may fail.
Programming Benchmarks
We have measured time necessary to program and verify PIC24EP512GP202.
Operation | FCKSM=0x | FCKSM=1x | Programming and Verification | 11.2s | 17.9s | Programming only | 10.2s | 10.2s | Verification only | 8.6s | 8.6s |
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The measurements reflect the time necessary to program/verify the entire chip, including all user programmable memory areas.
Debugging
NSDSP firmware contains all the necessary provisions for debugging PIC24EP512GP202 and may be debugged when debugging software becomes available.
PIC24EP512GP202 uses unordered halting, has 4 hardware breakpoints.
Debugging does not consume resources in the user space.
Links
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