PIC32MX564F128LPIC32MX570F512H PIC32MX570F512L PIC32MX575F256H PIC32MX575F256L PIC32MX575F512H PIC32MX575F512L PIC32MX664F064H PIC32MX664F064L PIC32MX664F128H PIC32MX664F128L PIC32MX675F256H PIC32MX675F256L PIC32MX675F512H PIC32MX675F512L PIC32MX695F512H PIC32MX695F512L PIC32MX764F128H PIC32MX764F128L PIC32MX775F256H PIC32MX775F256L PIC32MX775F512H PIC32MX775F512L PIC32MX795F512H PIC32MX795F512L
PIC32MX564F128L has more than one pair of PGECx and PGEDx pins. You can use any pair, but you must use them as a pair. For example, if PGEC2 is used for ICSPCLK, then ICSPDAT must be connected to PGED2.
All VSS and VDD pins must be connected. Even if one of these pins is not connected, programming may fail.
We have measured time necessary to program and verify PIC32MX564F128L.
|Operation||Time||Programming and Verification||3.1s||Programming only||2.8s||Verification only||2.4s|
The measurements reflect the time necessary to program/verify the entire chip, including all user programmable memory areas.
NSDSP firmware contains all the necessary provisions for debugging PIC32MX564F128L with NSDS. Once NSDS support for this device is compliete, NSDS will be able to debug it.
PIC32MX564F128L uses addresses 0xbfc00480 through 0xbfc00498 for debugging. This area is known as debugging vector. If there is any user code at this location, NSDSP will automatically overwrite it before debugging.
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